%0 Conference Paper %1 conf/vlsit/MertensHCZWMDRT23 %A Mertens, Hans %A Hosseini, M. %A Chiarella, Thomas %A Zhou, D. %A Wang, S. %A Mannaert, G. %A Dupuy, E. %A Radisic, D. %A Tao, Z. %A Oniki, Y. %A Hikavyy, Andriy %A Rosseel, R. %A Mingardi, A. %A Choudhury, S. %A Gowda, P. Puttarame %A Sebaai, F. %A Peter, A. %A Vandersmissen, Kevin %A Soulie, J. P. %A Keersgieter, An De %A Lima, L. Petersen Barbosa %A Cavalcante, C. %A Batuk, D. %A Martinez, G. T. %A Geypen, J. %A Seidel, F. %A Paulussen, K. %A Favia, P. %A Bömmels, Jürgen %A Loo, Roger %A Wong, P. %A Marquez, A. Sepulveda %A Chan, B. T. %A Mitard, Jérôme %A Subramanian, S. %A Demuynck, S. %A Litta, E. Dentoni %A Horiguchi, N. %A Samavedam, S. %A Biesemans, S. %B VLSI Technology and Circuits %D 2023 %I IEEE %K dblp %P 1-2 %T Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. %U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#MertensHCZWMDRT23 %@ 978-4-86348-806-9

@inproceedings{conf/vlsit/MertensHCZWMDRT23, added-at = {2023-09-30T00:00:00.000+0200}, author = {Mertens, Hans and Hosseini, M. and Chiarella, Thomas and Zhou, D. and Wang, S. and Mannaert, G. and Dupuy, E. and Radisic, D. and Tao, Z. and Oniki, Y. and Hikavyy, Andriy and Rosseel, R. and Mingardi, A. and Choudhury, S. and Gowda, P. Puttarame and Sebaai, F. and Peter, A. and Vandersmissen, Kevin and Soulie, J. P. and Keersgieter, An De and Lima, L. Petersen Barbosa and Cavalcante, C. and Batuk, D. and Martinez, G. T. and Geypen, J. and Seidel, F. and Paulussen, K. and Favia, P. and Bömmels, Jürgen and Loo, Roger and Wong, P. and Marquez, A. Sepulveda and Chan, B. T. and Mitard, Jérôme and Subramanian, S. and Demuynck, S. and Litta, E. Dentoni and Horiguchi, N. and Samavedam, S. and Biesemans, S.}, biburl = {https://www.bibsonomy.org/bibtex/2c1e465f51a84cc1d10c3593da81b27cb/dblp}, booktitle = {VLSI Technology and Circuits}, crossref = {conf/vlsit/2023}, ee = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185218}, interhash = {0ac4649968a0bb9d194ea3add463c3c9}, intrahash = {c1e465f51a84cc1d10c3593da81b27cb}, isbn = {978-4-86348-806-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-09T19:13:01.000+0200}, title = {Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.}, url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#MertensHCZWMDRT23}, year = 2023 }