Article,
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.
S. Rusu, S. Tam, H. Muljono, D. Ayers, J. Chang, B. Cherkauer, J. Stinson, J. Benoit, R. Varada, J. Leung, R. Limaye, and S. Vora.IEEE J. Solid State Circuits, 42 (1): 17-25 (2007)
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- 2007
- journal
- IEEE J. Solid State Circuits
- number
- 1
- pages
- 17-25
- volume
- 42
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- https://doi.org/10.1109/JSSC.2006.885041
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%1 journals/jssc/RusuTMACCSBVLLV07
%A Rusu, Stefan
%A Tam, Simon M.
%A Muljono, Harry
%A Ayers, David
%A Chang, Jonathan
%A Cherkauer, Brian S.
%A Stinson, Jason
%A Benoit, John
%A Varada, Raj
%A Leung, Justin
%A Limaye, Rahul Dilip
%A Vora, Sujal
%D 2007
%J IEEE J. Solid State Circuits
%K dblp
%N 1
%P 17-25
%T A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc42.html#RusuTMACCSBVLLV07
%V 42
@article{journals/jssc/RusuTMACCSBVLLV07,
added-at = {2020-08-30T00:00:00.000+0200},
author = {Rusu, Stefan and Tam, Simon M. and Muljono, Harry and Ayers, David and Chang, Jonathan and Cherkauer, Brian S. and Stinson, Jason and Benoit, John and Varada, Raj and Leung, Justin and Limaye, Rahul Dilip and Vora, Sujal},
biburl = {https://www.bibsonomy.org/bibtex/200f3e8c329f065a3d0c1049a59666cff/dblp},
ee = {https://doi.org/10.1109/JSSC.2006.885041},
interhash = {03c67897b73d42cffcda80999c7cb49f},
intrahash = {00f3e8c329f065a3d0c1049a59666cff},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
number = 1,
pages = {17-25},
timestamp = {2020-08-31T11:43:41.000+0200},
title = {A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc42.html#RusuTMACCSBVLLV07},
volume = 42,
year = 2007
}