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SOC Design Challenges in a Multi-threaded 65nm Dual Core Xeon® MP Processor., , , and . SoCC, page 217-220. IEEE, (2006)Power reduction techniques for an 8-core xeon® processor., , , , , , , , , and . ESSCIRC, page 340-343. IEEE, (2009)Design and integration methods for a multi-threaded dual core 65nm Xeon® processor., , , and . ICCAD, page 607-610. ACM, (2006)A 45nm 8-core enterprise Xeon® processor., , , , , , , , and . ISSCC, page 56-57. IEEE, (2009)A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 42 (1): 17-25 (2007)A 45 nm 8-Core Enterprise Xeon¯ Processor., , , , , , , , , and . IEEE J. Solid State Circuits, 45 (1): 7-14 (2010)A 22 nm 15-Core Enterprise Xeon® Processor Family., , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 35-48 (2015)5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family., , , , , , , , , and . ISSCC, page 102-103. IEEE, (2014)Computer Aided Turbine Blade Surface Design., , , and . ACM Annual Conference, page 65-73. ACM, (1985)