%0 Journal Article %1 journals/tcas/WangHLC12 %A Wang, Yu-Shun %A Hsieh, Min-Han %A Li, James Chien-Mo %A Chen, Charlie Chung-Ping %D 2012 %J IEEE Trans. Circuits Syst. I Regul. Pap. %K dblp %N 8 %P 1644-1655 %T An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example. %U http://dblp.uni-trier.de/db/journals/tcas/tcasI59.html#WangHLC12 %V 59-I

@article{journals/tcas/WangHLC12, added-at = {2020-05-22T00:00:00.000+0200}, author = {Wang, Yu-Shun and Hsieh, Min-Han and Li, James Chien-Mo and Chen, Charlie Chung-Ping}, biburl = {https://www.bibsonomy.org/bibtex/29fc384f2607a06d5d91ad39233b0380e/dblp}, ee = {https://doi.org/10.1109/TCSI.2012.2206503}, interhash = {07553f6dc4d657f5fca366c90d73a3a2}, intrahash = {9fc384f2607a06d5d91ad39233b0380e}, journal = {IEEE Trans. Circuits Syst. I Regul. Pap.}, keywords = {dblp}, number = 8, pages = {1644-1655}, timestamp = {2020-05-23T12:32:59.000+0200}, title = {An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasI59.html#WangHLC12}, volume = {59-I}, year = 2012 }