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An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example.

, , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (8): 1644-1655 (2012)

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Liang-Han Hsieh

Chi-Min Hsieh

Han Min Woo

Min-chü Han

Marianne Min-Jean Hsieh

 

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