%0 Conference Paper %1 conf/fpl/ZhaoYAIKS14 %A Zhao, Qian %A Yanagida, Kyosei %A Amagasaki, Motoki %A Iida, Masahiro %A Kuga, Morihiro %A Sueyoshi, Toshinori %B FPL %D 2014 %I IEEE %K dblp %P 1-6 %T A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2014.html#ZhaoYAIKS14

@inproceedings{conf/fpl/ZhaoYAIKS14, added-at = {2017-10-18T00:00:00.000+0200}, author = {Zhao, Qian and Yanagida, Kyosei and Amagasaki, Motoki and Iida, Masahiro and Kuga, Morihiro and Sueyoshi, Toshinori}, biburl = {https://www.bibsonomy.org/bibtex/2373e60cbd4a75480abe45459560f8455/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2014}, ee = {https://doi.org/10.1109/FPL.2014.6927460}, interhash = {0acf5bd5981329eb29ce14e3073a564c}, intrahash = {373e60cbd4a75480abe45459560f8455}, keywords = {dblp}, pages = {1-6}, publisher = {IEEE}, timestamp = {2019-10-17T19:13:37.000+0200}, title = {A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2014.html#ZhaoYAIKS14}, year = 2014 }