@article{journals/jssc/HungCYKLSHHLSHC15,
added-at = {2021-10-14T00:00:00.000+0200},
author = {Hung, Chun-Hsiung and Chang, Meng-Fan and Yang, Yih-Shan and Kuo, Yao-Jen and Lai, Tzu-Neng and Shen, Shin-Jang and Hsu, Jo-Yu and Hung, Shuo-Nan and Lue, Hang-Ting and Shih, Yen-Hao and Huang, Shih-Lin and Chen, Ti-Wen and Chen, Tzung Shen and Chen, Chung Kuang and Hung, Chi-Yu and Lu, Chih-Yuan},
biburl = {https://www.bibsonomy.org/bibtex/201dab515a0fb62cf472e3dda71abc7c9/dblp},
ee = {https://doi.org/10.1109/JSSC.2015.2413841},
interhash = {0df3723f50417b74af68d0f60e21d962},
intrahash = {01dab515a0fb62cf472e3dda71abc7c9},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
number = 6,
pages = {1491-1501},
timestamp = {2024-04-08T10:44:42.000+0200},
title = {Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc50.html#HungCYKLSHHLSHC15},
volume = 50,
year = 2015
}