There are many different ways that an application is executed on a Reconfigurable System-on-a-Chip (RSoC). They can significantly impact the overall system energy dissipation. In this paper, we propose a three-step design process for application synthesis using RSoCs. We develop (a) a performance model to abstract a general class of RSoC architectures for application development, (b) a mathematical formulation of the energy-efficient synthesis problem for a class of applications and (c) a dynamic programming algorithm that minimises the system energy dissipation. Using the proposed design process, reduction in energy dissipation ranging from 41% to 54% is observed in our experiments.
%0 Journal Article
%1 ou05energy
%A Ou, J.
%A Choi, S. B.
%A Prasanna, V. K.
%B International Journal of Embedded Systems
%D 2005
%J International Journal of Embedded Systems
%K CoDesign Efficient Energy IJES Reconfigurable SoC Synthesis
%P 91 - 102
%T Energy-Efficient Hardware/software Co-Synthesis for a Class of Applications on Reconfigurable SoCs
%U http://doi.acm.org/10.1504/IJES.2005.008811
%V 1
%X There are many different ways that an application is executed on a Reconfigurable System-on-a-Chip (RSoC). They can significantly impact the overall system energy dissipation. In this paper, we propose a three-step design process for application synthesis using RSoCs. We develop (a) a performance model to abstract a general class of RSoC architectures for application development, (b) a mathematical formulation of the energy-efficient synthesis problem for a class of applications and (c) a dynamic programming algorithm that minimises the system energy dissipation. Using the proposed design process, reduction in energy dissipation ranging from 41% to 54% is observed in our experiments.
@article{ou05energy,
abstract = {There are many different ways that an application is executed on a Reconfigurable System-on-a-Chip (RSoC). They can significantly impact the overall system energy dissipation. In this paper, we propose a three-step design process for application synthesis using RSoCs. We develop (a) a performance model to abstract a general class of RSoC architectures for application development, (b) a mathematical formulation of the energy-efficient synthesis problem for a class of applications and (c) a dynamic programming algorithm that minimises the system energy dissipation. Using the proposed design process, reduction in energy dissipation ranging from 41% to 54% is observed in our experiments.},
added-at = {2007-04-12T13:24:49.000+0200},
author = {Ou, J. and Choi, S. B. and Prasanna, V. K.},
biburl = {https://www.bibsonomy.org/bibtex/22313732c6bf8df2df9930d30fe362168/derkling},
booktitle = {International Journal of Embedded Systems},
hardcopy = {No},
interhash = {104d542961e7a735c634dd30b78b0618},
intrahash = {2313732c6bf8df2df9930d30fe362168},
journal = {International Journal of Embedded Systems},
keywords = {CoDesign Efficient Energy IJES Reconfigurable SoC Synthesis},
local = {./AllPapers/2005_IJES_ou05energy.pdf},
pages = {91 - 102},
timestamp = {2007-04-12T13:24:49.000+0200},
title = {Energy-Efficient Hardware/software Co-Synthesis for a Class of Applications on Reconfigurable SoCs},
url = {http://doi.acm.org/10.1504/IJES.2005.008811},
volume = 1,
year = 2005
}