%0 Conference Paper %1 conf/cicc/KuoTYLWWD13 %A Kuo, Ming-Zhang %A Takahashi, Osamu %A Yang, Ping-Lin %A Lin, Cheng-Chung %A Wang, Min-Jer %A Wang, Ping-Wei %A Dhong, Sang H. %B CICC %D 2013 %I IEEE %K dblp %P 1-4 %T A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm2 per MB. %U http://dblp.uni-trier.de/db/conf/cicc/cicc2013.html#KuoTYLWWD13

@inproceedings{conf/cicc/KuoTYLWWD13, added-at = {2017-05-17T00:00:00.000+0200}, author = {Kuo, Ming-Zhang and Takahashi, Osamu and Yang, Ping-Lin and Lin, Cheng-Chung and Wang, Min-Jer and Wang, Ping-Wei and Dhong, Sang H.}, biburl = {https://www.bibsonomy.org/bibtex/24683754e7f43ad808f2230adb78f88db/dblp}, booktitle = {CICC}, crossref = {conf/cicc/2013}, ee = {https://doi.org/10.1109/CICC.2013.6658452}, interhash = {21e6e0b9e2a65f85c8d0ff63e9709a4b}, intrahash = {4683754e7f43ad808f2230adb78f88db}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2019-10-17T23:08:27.000+0200}, title = {A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm2 per MB.}, url = {http://dblp.uni-trier.de/db/conf/cicc/cicc2013.html#KuoTYLWWD13}, year = 2013 }