%0 Conference Paper %1 conf/iscas/WuB02 %A Wu, Jian-Yi %A Bibyk, Steven B. %B ISCAS (5) %D 2002 %I IEEE %K dblp %P 229-232 %T Robust design with virtual tests of mixed-signal circuits in VHDL-AMS. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2002-5.html#WuB02 %@ 0-7803-7448-7

@inproceedings{conf/iscas/WuB02, added-at = {2016-05-20T00:00:00.000+0200}, author = {Wu, Jian-Yi and Bibyk, Steven B.}, biburl = {https://www.bibsonomy.org/bibtex/287501216ed7f24b6f2e65efa3f12dfac/dblp}, booktitle = {ISCAS (5)}, crossref = {conf/iscas/2002}, ee = {http://dx.doi.org/10.1109/ISCAS.2002.1010682}, interhash = {254679950ae134632a11ad78153b47d0}, intrahash = {87501216ed7f24b6f2e65efa3f12dfac}, isbn = {0-7803-7448-7}, keywords = {dblp}, pages = {229-232}, publisher = {IEEE}, timestamp = {2016-05-21T12:03:45.000+0200}, title = {Robust design with virtual tests of mixed-signal circuits in VHDL-AMS.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2002-5.html#WuB02}, year = 2002 }