%0 Journal Article %1 journals/ieicet/HuangCLH11 %A Huang, Juinn-Dar %A Chen, Chia-I %A Lin, Yen-Ting %A Hsu, Wan-Ling %D 2011 %J IEICE Trans. Fundam. Electron. Commun. Comput. Sci. %K dblp %N 4 %P 1151-1155 %T Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet94a.html#HuangCLH11 %V 94-A

@article{journals/ieicet/HuangCLH11, added-at = {2020-06-15T00:00:00.000+0200}, author = {Huang, Juinn-Dar and Chen, Chia-I and Lin, Yen-Ting and Hsu, Wan-Ling}, biburl = {https://www.bibsonomy.org/bibtex/2cfb88e8e09661be8389eb9a2c6139231/dblp}, ee = {http://search.ieice.org/bin/summary.php?id=e94-a_4_1151}, interhash = {15d8e1f76be5ff52eb85a23026e5d280}, intrahash = {cfb88e8e09661be8389eb9a2c6139231}, journal = {IEICE Trans. Fundam. Electron. Commun. Comput. Sci.}, keywords = {dblp}, number = 4, pages = {1151-1155}, timestamp = {2020-06-16T11:47:56.000+0200}, title = {Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet94a.html#HuangCLH11}, volume = {94-A}, year = 2011 }