%0 Conference Paper %1 conf/arc/SantosTBTK17 %A dos Santos, André Flores %A Tambara, Lucas Antunes %A Benevenuti, Fabio %A Tonfat, Jorge L. %A Kastensmidt, Fernanda Lima %B ARC %D 2017 %E Wong, Stephan %E Beck, Antonio Carlos Schneider %E Bertels, Koen %E Carro, Luigi %K dblp %P 202-213 %T Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs. %U http://dblp.uni-trier.de/db/conf/arc/arc2017.html#SantosTBTK17 %V 10216 %@ 978-3-319-56258-2

@inproceedings{conf/arc/SantosTBTK17, added-at = {2019-09-25T00:00:00.000+0200}, author = {dos Santos, André Flores and Tambara, Lucas Antunes and Benevenuti, Fabio and Tonfat, Jorge L. and Kastensmidt, Fernanda Lima}, biburl = {https://www.bibsonomy.org/bibtex/218dfc11613e93f5a44e67b2ecff55065/dblp}, booktitle = {ARC}, crossref = {conf/arc/2017}, editor = {Wong, Stephan and Beck, Antonio Carlos Schneider and Bertels, Koen and Carro, Luigi}, ee = {https://doi.org/10.1007/978-3-319-56258-2_18}, interhash = {67ec4cbc08630805eb36521a0bb74ce0}, intrahash = {18dfc11613e93f5a44e67b2ecff55065}, isbn = {978-3-319-56258-2}, keywords = {dblp}, pages = {202-213}, series = {Lecture Notes in Computer Science}, timestamp = {2019-09-26T14:06:35.000+0200}, title = {Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs.}, url = {http://dblp.uni-trier.de/db/conf/arc/arc2017.html#SantosTBTK17}, volume = 10216, year = 2017 }