%0 Journal Article %1 journals/jssc/FuketaNTS14 %A Fuketa, Hiroshi %A Nomura, Masahiro %A Takamiya, Makoto %A Sakurai, Takayasu %D 2014 %J IEEE J. Solid State Circuits %K dblp %N 2 %P 536-544 %T Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits. %U http://dblp.uni-trier.de/db/journals/jssc/jssc49.html#FuketaNTS14 %V 49

@article{journals/jssc/FuketaNTS14, added-at = {2020-08-30T00:00:00.000+0200}, author = {Fuketa, Hiroshi and Nomura, Masahiro and Takamiya, Makoto and Sakurai, Takayasu}, biburl = {https://www.bibsonomy.org/bibtex/2945b726af06c286a1e13a17848db7045/dblp}, ee = {https://doi.org/10.1109/JSSC.2013.2294172}, interhash = {9786579c233e3d1fb0c17bdf21aa1940}, intrahash = {945b726af06c286a1e13a17848db7045}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 2, pages = {536-544}, timestamp = {2020-08-31T11:44:12.000+0200}, title = {Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc49.html#FuketaNTS14}, volume = 49, year = 2014 }