%0 Journal Article %1 journals/jssc/BertulessiKCGSL19 %A Bertulessi, Luca %A Karman, Saleh %A Cherniak, Dmytro %A Garghetti, Alessandro %A Samori, Carlo %A Lacaita, Andrea L. %A Levantino, Salvatore %D 2019 %J IEEE J. Solid State Circuits %K dblp %N 12 %P 3493-3502 %T A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS. %U http://dblp.uni-trier.de/db/journals/jssc/jssc54.html#BertulessiKCGSL19 %V 54

@article{journals/jssc/BertulessiKCGSL19, added-at = {2020-10-26T00:00:00.000+0100}, author = {Bertulessi, Luca and Karman, Saleh and Cherniak, Dmytro and Garghetti, Alessandro and Samori, Carlo and Lacaita, Andrea L. and Levantino, Salvatore}, biburl = {https://www.bibsonomy.org/bibtex/20856beca49e6a8d5a0b3ce4c072f0148/dblp}, ee = {https://doi.org/10.1109/JSSC.2019.2940332}, interhash = {c49453cbe9ff194c918753f0ff5831e2}, intrahash = {0856beca49e6a8d5a0b3ce4c072f0148}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 12, pages = {3493-3502}, timestamp = {2020-10-27T11:39:56.000+0100}, title = {A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc54.html#BertulessiKCGSL19}, volume = 54, year = 2019 }