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Disambiguation of "Karman, Saleh"

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A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS.

, , , , , , and . IEEE J. Solid State Circuits, 54 (12): 3493-3502 (2019)

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Karman Raabe

Saleh Ba-Saleh

Ahmad Muhammad Saleh

Bahman Salehin

Nabil Ahmed Saleh

 

Other publications of authors with the same name

Jitter Minimization in Digital PLLs with Mid-Rise TDCs., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (3): 743-752 (2020)Multi-core frequency synthesizers for MM-wave communications.. Polytechnic University of Milan, Italy, (2021)32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , , , and 5 other author(s). ISSCC, page 456-458. IEEE, (2021)A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter., , , , , , , , , and 4 other author(s). ISSCC, page 445-447. IEEE, (2021)A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS., , , , , , and . IEEE J. Solid State Circuits, 54 (12): 3493-3502 (2019)A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS., , , , , , , and . ISSCC, page 268-270. IEEE, (2019)A Novel Topology of Coupled Phase-Locked Loops., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (3): 989-997 (2021)A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 57 (6): 1723-1735 (2022)