%0 Conference Paper %1 conf/cicc/HiienkariTKTK14 %A Hiienkari, Markus %A Teittinen, Jukka %A Koskinen, Lauri %A Turnquist, Matthew J. %A Kaltiokallio, Mikko %B CICC %D 2014 %I IEEE %K dblp %P 1-4 %T A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS. %U http://dblp.uni-trier.de/db/conf/cicc/cicc2014.html#HiienkariTKTK14

@inproceedings{conf/cicc/HiienkariTKTK14, added-at = {2017-05-17T00:00:00.000+0200}, author = {Hiienkari, Markus and Teittinen, Jukka and Koskinen, Lauri and Turnquist, Matthew J. and Kaltiokallio, Mikko}, biburl = {https://www.bibsonomy.org/bibtex/2f04a81a96994a5e9cfc2e5121734be2b/dblp}, booktitle = {CICC}, crossref = {conf/cicc/2014}, ee = {https://doi.org/10.1109/CICC.2014.6946095}, interhash = {de9fb7e1f6d2edaca30b4020feb2f2d8}, intrahash = {f04a81a96994a5e9cfc2e5121734be2b}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2019-10-17T23:08:13.000+0200}, title = {A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/cicc/cicc2014.html#HiienkariTKTK14}, year = 2014 }