%0 Conference Paper %1 conf/vlsi-dat/LiangHPR12 %A Liang, Guixuan %A He, Danping %A Portilla, Jorge %A Riesgo, Teresa %B VLSI-DAT %D 2012 %I IEEE %K dblp %P 1-4 %T A hardware in the loop design methodology for FPGA system and its application to complex functions. %U http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2012.html#LiangHPR12 %@ 978-1-4577-2080-2

@inproceedings{conf/vlsi-dat/LiangHPR12, added-at = {2015-09-29T00:00:00.000+0200}, author = {Liang, Guixuan and He, Danping and Portilla, Jorge and Riesgo, Teresa}, biburl = {https://www.bibsonomy.org/bibtex/277fb212af1020f8893661c5b5b8d4257/dblp}, booktitle = {VLSI-DAT}, crossref = {conf/vlsi-dat/2012}, ee = {http://dx.doi.org/10.1109/VLSI-DAT.2012.6212666}, interhash = {f1512c1b38710e925e173696f01b2e92}, intrahash = {77fb212af1020f8893661c5b5b8d4257}, isbn = {978-1-4577-2080-2}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2015-09-30T11:34:11.000+0200}, title = {A hardware in the loop design methodology for FPGA system and its application to complex functions.}, url = {http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2012.html#LiangHPR12}, year = 2012 }