%0 Journal Article %1 journals/jssc/KirihataGHDWPJW98 %A Kirihata, Toshiaki %A Gall, Martin %A Hosokawa, Kohji %A Dortu, Jean-Marc %A Wong, Hing %A Pfefferl, Peter %A Ji, Brian L. %A Weinfurtner, Oliver %A DeBrosse, John K. %A Terletzki, Hartmud %A Selz, Manfred %A Ellis, Wayne %A Wordeman, Matthew R. %A Kiehl, Oliver %D 1998 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 1711-1719 %T A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture. %U http://dblp.uni-trier.de/db/journals/jssc/jssc33.html#KirihataGHDWPJW98 %V 33

@article{journals/jssc/KirihataGHDWPJW98, added-at = {2022-07-06T00:00:00.000+0200}, author = {Kirihata, Toshiaki and Gall, Martin and Hosokawa, Kohji and Dortu, Jean-Marc and Wong, Hing and Pfefferl, Peter and Ji, Brian L. and Weinfurtner, Oliver and DeBrosse, John K. and Terletzki, Hartmud and Selz, Manfred and Ellis, Wayne and Wordeman, Matthew R. and Kiehl, Oliver}, biburl = {https://www.bibsonomy.org/bibtex/25fe00af4c8f8f2b3a748421df82b6c8e/dblp}, ee = {https://doi.org/10.1109/4.726565}, interhash = {f1c8f312c87247ae4a78c733de774034}, intrahash = {5fe00af4c8f8f2b3a748421df82b6c8e}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {1711-1719}, timestamp = {2024-04-08T10:42:20.000+0200}, title = {A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc33.html#KirihataGHDWPJW98}, volume = 33, year = 1998 }