%0 Conference Paper %1 conf/iastedCCS/VasudevanPL04 %A Vasudevan, Dilip P. %A Parkerson, James Patrick %A Lala, Parag K. %B Circuits, Signals, and Systems %D 2004 %E Rashid, M. H. %I IASTED/ACTA Press %K dblp %P 452-456 %T Logic implementation using a reversible gate. %U http://dblp.uni-trier.de/db/conf/iastedCCS/iastedCCS2004.html#VasudevanPL04

@inproceedings{conf/iastedCCS/VasudevanPL04, added-at = {2010-07-21T16:13:05.000+0200}, author = {Vasudevan, Dilip P. and Parkerson, James Patrick and Lala, Parag K.}, biburl = {https://www.bibsonomy.org/bibtex/242130fb05f27508e74b1cdbee11cec36/dblp}, booktitle = {Circuits, Signals, and Systems}, crossref = {conf/iastedCCS/2004}, date = {2010-05-25}, editor = {Rashid, M. H.}, interhash = {f475339967f9cb7609c0b9da861190e8}, intrahash = {42130fb05f27508e74b1cdbee11cec36}, keywords = {dblp}, pages = {452-456}, publisher = {IASTED/ACTA Press}, timestamp = {2010-07-21T16:13:05.000+0200}, title = {Logic implementation using a reversible gate.}, url = {http://dblp.uni-trier.de/db/conf/iastedCCS/iastedCCS2004.html#VasudevanPL04}, year = 2004 }