%0 Conference Paper %1 conf/fpl/SchumacherJKBF11 %A Schumacher, Paul %A Jha, Pradip %A Kuntur, Sudha %A Burke, Tim %A Frost, Alan %B FPL %D 2011 %I IEEE Computer Society %K dblp %P 343-348 %T Fast RTL Power Estimation for FPGA Designs. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2011.html#SchumacherJKBF11 %@ 978-1-4577-1484-9

@inproceedings{conf/fpl/SchumacherJKBF11, added-at = {2023-03-24T00:00:00.000+0100}, author = {Schumacher, Paul and Jha, Pradip and Kuntur, Sudha and Burke, Tim and Frost, Alan}, biburl = {https://www.bibsonomy.org/bibtex/276435462dc0710da3cfc8f171a9562d0/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2011}, ee = {https://doi.ieeecomputersociety.org/10.1109/FPL.2011.68}, interhash = {fb7773afe9431fad4bea95bfd4e50373}, intrahash = {76435462dc0710da3cfc8f171a9562d0}, isbn = {978-1-4577-1484-9}, keywords = {dblp}, pages = {343-348}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T14:51:39.000+0200}, title = {Fast RTL Power Estimation for FPGA Designs.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2011.html#SchumacherJKBF11}, year = 2011 }