%0 Conference Paper %1 conf/aspdac/PhamABBGHHJKKKLLNPPPPRVWWW06 %A Pham, Dac C. %A Anderson, Hans-Werner %A Behnen, Erwin %A Bolliger, Mark %A Gupta, Sanjay %A Hofstee, H. Peter %A Harvey, Paul E. %A Johns, Charles R. %A Kahle, James A. %A Kameyama, Atsushi %A Keaty, John M. %A Le, Bob %A Lee, Sang %A Nguyen, Tuyen V. %A Petrovick, John G. %A Pham, Mydung %A Pille, Juergen %A Posluszny, Stephen D. %A Riley, Mack W. %A Verock, Joseph %A Warnock, James D. %A Weitzel, Steve %A Wendel, Dieter F. %B ASP-DAC %D 2006 %E Hirose, Fumiyasu %I IEEE %K dblp %P 871-878 %T Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2006.html#PhamABBGHHJKKKLLNPPPPRVWWW06 %@ 0-7803-9451-8

@inproceedings{conf/aspdac/PhamABBGHHJKKKLLNPPPPRVWWW06, added-at = {2021-10-15T00:00:00.000+0200}, author = {Pham, Dac C. and Anderson, Hans-Werner and Behnen, Erwin and Bolliger, Mark and Gupta, Sanjay and Hofstee, H. Peter and Harvey, Paul E. and Johns, Charles R. and Kahle, James A. and Kameyama, Atsushi and Keaty, John M. and Le, Bob and Lee, Sang and Nguyen, Tuyen V. and Petrovick, John G. and Pham, Mydung and Pille, Juergen and Posluszny, Stephen D. and Riley, Mack W. and Verock, Joseph and Warnock, James D. and Weitzel, Steve and Wendel, Dieter F.}, biburl = {https://www.bibsonomy.org/bibtex/2e49018b12e51855a3f3165d2653fcc12/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2006}, editor = {Hirose, Fumiyasu}, ee = {https://doi.org/10.1145/1118299.1118497}, interhash = {20e7dfb46867b1c2c02ae25640f697f4}, intrahash = {e49018b12e51855a3f3165d2653fcc12}, isbn = {0-7803-9451-8}, keywords = {dblp}, pages = {871-878}, publisher = {IEEE}, timestamp = {2024-04-10T04:16:41.000+0200}, title = {Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2006.html#PhamABBGHHJKKKLLNPPPPRVWWW06}, year = 2006 }