In this paper, an architecture designed for Non-
Maximal Suppression used in Canny edge detection algorithm
is presented in order to reduce memory requirements
significantly. The architecture also achieves decreased latency
and increased throughput with no loss in edge detection. The
new algorithm used has a low-complexity 8-bin non-uniform
gradient magnitude histogram to compute block-based
hysteresis thresholds that are used by the Canny edge detector.
Furthermore, the hardware architecture of the proposed
algorithm is presented in this paper and the architecture is
synthesized on the Xilinx Virtex 5 FPGA. The design
development is done in VHDL and simulated results are
obtained using modelsim 6.3 with Xilinx 12.2.
%0 Generic
%1 chandrashekarns2013thresholding
%A Chandrashekar N.S., Dr. K.R. Nataraj
%B 2013 Mobile Communication - I
%D 2013
%E Kaushik, Dr. B K
%I ACEEE (A Computer division of IDES)
%K Canny Detector Distributed Edge Processing
%T NMS and Thresholding Architecture used for FPGA based Canny Edge Detector for Area Optimization
%U http://searchdl.org/public/book_series/LSCS/2/26.pdf
%X In this paper, an architecture designed for Non-
Maximal Suppression used in Canny edge detection algorithm
is presented in order to reduce memory requirements
significantly. The architecture also achieves decreased latency
and increased throughput with no loss in edge detection. The
new algorithm used has a low-complexity 8-bin non-uniform
gradient magnitude histogram to compute block-based
hysteresis thresholds that are used by the Canny edge detector.
Furthermore, the hardware architecture of the proposed
algorithm is presented in this paper and the architecture is
synthesized on the Xilinx Virtex 5 FPGA. The design
development is done in VHDL and simulated results are
obtained using modelsim 6.3 with Xilinx 12.2.
@conference{chandrashekarns2013thresholding,
abstract = { In this paper, an architecture designed for Non-
Maximal Suppression used in Canny edge detection algorithm
is presented in order to reduce memory requirements
significantly. The architecture also achieves decreased latency
and increased throughput with no loss in edge detection. The
new algorithm used has a low-complexity 8-bin non-uniform
gradient magnitude histogram to compute block-based
hysteresis thresholds that are used by the Canny edge detector.
Furthermore, the hardware architecture of the proposed
algorithm is presented in this paper and the architecture is
synthesized on the Xilinx Virtex 5 FPGA. The design
development is done in VHDL and simulated results are
obtained using modelsim 6.3 with Xilinx 12.2.},
added-at = {2014-02-05T07:01:34.000+0100},
author = {Chandrashekar N.S., Dr. K.R. Nataraj},
biburl = {https://www.bibsonomy.org/bibtex/219cf2e07adb9bd1c11b82c5bc4474ac5/idescitation},
booktitle = {2013 Mobile Communication - I},
editor = {Kaushik, Dr. B K},
interhash = {24850224a423d47736545dd48a3c9fa9},
intrahash = {19cf2e07adb9bd1c11b82c5bc4474ac5},
keywords = {Canny Detector Distributed Edge Processing},
organization = {Institute of Doctors Engineers Scientists},
publisher = {ACEEE (A Computer division of IDES)},
timestamp = {2014-02-05T07:01:34.000+0100},
title = {NMS and Thresholding Architecture used for FPGA based Canny Edge Detector for Area Optimization},
url = {http://searchdl.org/public/book_series/LSCS/2/26.pdf},
year = 2013
}