%0 Conference Paper %1 conf/isqed/IizukaIA04 %A Iizuka, Tetsuya %A Ikeda, Makoto %A Asada, Kunihiro %B ISQED %D 2004 %I IEEE Computer Society %K dblp %P 377-380 %T Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. %U http://dblp.uni-trier.de/db/conf/isqed/isqed2004.html#IizukaIA04 %@ 0-7695-2093-6

@inproceedings{conf/isqed/IizukaIA04, added-at = {2023-03-23T00:00:00.000+0100}, author = {Iizuka, Tetsuya and Ikeda, Makoto and Asada, Kunihiro}, biburl = {https://www.bibsonomy.org/bibtex/2c60773ffb752c8d1e7b417143f1086ef/dblp}, booktitle = {ISQED}, crossref = {conf/isqed/2004}, ee = {https://doi.ieeecomputersociety.org/10.1109/ISQED.2004.1283703}, interhash = {21f75523ae6cf0da45c7dd1ecc329705}, intrahash = {c60773ffb752c8d1e7b417143f1086ef}, isbn = {0-7695-2093-6}, keywords = {dblp}, pages = {377-380}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T14:10:25.000+0200}, title = {Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells.}, url = {http://dblp.uni-trier.de/db/conf/isqed/isqed2004.html#IizukaIA04}, year = 2004 }