%0 Journal Article %1 journals/mr/GaoLBCWV03 %A Gao, Xiaofang %A Liou, Juin J. %A Bernier, Joe %A Croft, Gregg D. %A Wong, Waisum %A Vishwanathan, Satya %D 2003 %J Microelectron. Reliab. %K dblp %N 5 %P 725-733 %T Optimization of on-chip ESD protection structures for minimal parasitic capacitance. %U http://dblp.uni-trier.de/db/journals/mr/mr43.html#GaoLBCWV03 %V 43

@article{journals/mr/GaoLBCWV03, added-at = {2020-02-22T00:00:00.000+0100}, author = {Gao, Xiaofang and Liou, Juin J. and Bernier, Joe and Croft, Gregg D. and Wong, Waisum and Vishwanathan, Satya}, biburl = {https://www.bibsonomy.org/bibtex/22e99aa8ebf562c35bf92b458d5effec9/dblp}, ee = {https://doi.org/10.1016/S0026-2714(03)00026-X}, interhash = {8bced6fb78b673f3060cf69733a43cfa}, intrahash = {2e99aa8ebf562c35bf92b458d5effec9}, journal = {Microelectron. Reliab.}, keywords = {dblp}, number = 5, pages = {725-733}, timestamp = {2020-02-25T13:25:44.000+0100}, title = {Optimization of on-chip ESD protection structures for minimal parasitic capacitance.}, url = {http://dblp.uni-trier.de/db/journals/mr/mr43.html#GaoLBCWV03}, volume = 43, year = 2003 }