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JFET circuit simulation using SPICE implemented with an improved model., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (1): 105-109 (1994)Characterization and modeling of flicker noise in junction field-effect transistor with source and drain trench isolation., , и . Microelectron. Reliab., 47 (1): 46-50 (2007)Editorial., , и . Microelectron. Reliab., 55 (11): 2173 (2015)Optimization of on-chip ESD protection structures for minimal parasitic capacitance., , , , , и . Microelectron. Reliab., 43 (5): 725-733 (2003)vfTLP-VTH: A new method for quantifying the effectiveness of ESD protection for the CDM classification test., , , , и . Microelectron. Reliab., 53 (2): 196-204 (2013)Influence of polysilicon-gate depletion on the subthreshold behavior of submicron MOSFETs., , , , , , , и . Microelectron. Reliab., 42 (3): 343-347 (2002)Integration-based approach to evaluate the sub-threshold slope of MOSFETs., , , и . Microelectron. Reliab., 50 (2): 312-315 (2010)InGaP/GaAs heterojunction bipolar transistor and RF power amplifier reliability., , и . Microelectron. Reliab., 48 (8-9): 1212-1215 (2008)Editorial., и . Microelectron. Reliab., 50 (5): 583 (2010)Novel ESD protection solution for single-ended mixer in GaAs pHEMT technology., , и . Microelectron. Reliab., 53 (7): 952-955 (2013)