%0 Conference Paper %1 conf/icip/PalominoSABS12 %A Palomino, Daniel %A Sampaio, Felipe %A Agostini, Luciano Volcan %A Bampi, Sergio %A Susin, Altamiro Amadeu %B ICIP %D 2012 %I IEEE %K dblp %P 201-204 %T A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard. %U http://dblp.uni-trier.de/db/conf/icip/icip2012.html#PalominoSABS12 %@ 978-1-4673-2534-9

@inproceedings{conf/icip/PalominoSABS12, added-at = {2022-04-09T00:00:00.000+0200}, author = {Palomino, Daniel and Sampaio, Felipe and Agostini, Luciano Volcan and Bampi, Sergio and Susin, Altamiro Amadeu}, biburl = {https://www.bibsonomy.org/bibtex/26fda455c2ebed1b5d886500ae560474e/dblp}, booktitle = {ICIP}, crossref = {conf/icip/2012}, ee = {https://doi.org/10.1109/ICIP.2012.6466830}, interhash = {2b760c0fb2fd1cb53e52b5945df3b815}, intrahash = {6fda455c2ebed1b5d886500ae560474e}, isbn = {978-1-4673-2534-9}, keywords = {dblp}, pages = {201-204}, publisher = {IEEE}, timestamp = {2024-04-10T15:45:37.000+0200}, title = {A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard.}, url = {http://dblp.uni-trier.de/db/conf/icip/icip2012.html#PalominoSABS12}, year = 2012 }