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A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard.

D. Palomino, F. Sampaio, L. Agostini, S. Bampi, and A. Susin. ICIP, page 201-204. IEEE, (2012)

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Leonardo Sampaio

Erica Sampaio

Augusto Sampaio

Diogo Sampaio

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Transforms and quantization design targeting the H.264/AVC intra prediction constraints.R. Dornelles, F. Sampaio, D. Palomino, and L. Agostini. SBCCI, ACM, (2009)A multitransform architecture for the H.264/AVC standard and its design space exploration.F. Sampaio, R. Dornelles, D. Palomino, G. Siedler, M. Corrêa, and L. Agostini. ICECS, page 711-714. IEEE, (2009)Video Decoder Improvements with Near-Data Speculative Motion Compensation Processing.G. de Souza, J. Azambuja, B. Zatt, M. Alves, S. Bampi, and F. Sampaio. ISCAS, page 399-403. IEEE, (2022)Memory Assessment Of Versatile Video Coding.A. Cerveira, L. Agostini, B. Zatt, and F. Sampaio. ICIP, page 1186-1190. IEEE, (2020)Memory-aware multiple reference frame motion estimation for the H.264/AVC standard.M. Grellert, F. Sampaio, B. Hecktheuer, J. de Mattos, and L. Agostini. ICECS, page 575-578. IEEE, (2010)Evaluation of Cache-Based Memory Hierarchy for HEVC Video Decoding.G. de Souza, S. Bampi, A. Cerveira, B. Zatt, and F. Sampaio. SBCCI, page 1-6. IEEE, (2020)An UHD 4K@60fps Deblocking Filter Hardware Targeting the AV1 Decoder.E. Zummach, R. Palau, J. Goebel, F. Sampaio, G. Corrêa, L. Agostini, and M. Porto. ICECS, page 1-4. IEEE, (2020)Error Resilience Evaluation of Approximate Storage in the Motion Compensation of VVC Decoders.R. Soares, M. Isquierdo, F. Sampaio, A. Rahmani, N. Dutt, G. Corrêa, D. Palomino, and B. Zatt. LASCAS, page 1-4. IEEE, (2023)Error Resilience Evaluation of Approximate Storage in the Intra Prediction of VVC Decoders.M. Isquierdo, R. Soares, F. Sampaio, B. Zatt, and D. Palomino. SBCCI, page 1-6. IEEE, (2022)Variable block size motion estimation architecture with a fast bottom-up decision mode and an integrated motion compensation targeting the H.264/AVC video coding standard.R. Dornelles, F. Sampaio, and L. Agostini. SBCCI, page 186-191. ACM, (2010)

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Disambiguation of "Sampaio, Felipe"

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A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard.

Please choose a person to relate this publication to

Leonardo Sampaio

Erica Sampaio

Augusto Sampaio

Augusto Sampaio

Diogo Sampaio

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sampaio, Felipe"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard.

Please choose a person to relate this publication to

Leonardo Sampaio

Erica Sampaio

Augusto Sampaio

Augusto Sampaio

Diogo Sampaio

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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MSOffice XML

A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard.