%0 Conference Paper %1 conf/isscc/BolSMHXFDSF19 %A Bol, David %A Schramme, Maxime %A Moreau, Ludovic %A Haine, Thomas %A Xu, Pengcheng %A Frenkel, Charlotte %A Dekimpe, Remi %A Stas, François %A Flandre, Denis %B ISSCC %D 2019 %I IEEE %K dblp %P 322-324 %T A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode. %U http://dblp.uni-trier.de/db/conf/isscc/isscc2019.html#BolSMHXFDSF19 %@ 978-1-5386-8531-0

@inproceedings{conf/isscc/BolSMHXFDSF19, added-at = {2023-10-25T00:00:00.000+0200}, author = {Bol, David and Schramme, Maxime and Moreau, Ludovic and Haine, Thomas and Xu, Pengcheng and Frenkel, Charlotte and Dekimpe, Remi and Stas, François and Flandre, Denis}, biburl = {https://www.bibsonomy.org/bibtex/2c27d99b3c124585872950ef475e554a8/dblp}, booktitle = {ISSCC}, crossref = {conf/isscc/2019}, ee = {https://doi.org/10.1109/ISSCC.2019.8662293}, interhash = {948fca588251ecc43ea9eb53d0fb5c89}, intrahash = {c27d99b3c124585872950ef475e554a8}, isbn = {978-1-5386-8531-0}, keywords = {dblp}, pages = {322-324}, publisher = {IEEE}, timestamp = {2024-04-10T11:04:02.000+0200}, title = {A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode.}, url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2019.html#BolSMHXFDSF19}, year = 2019 }