Modern and future AI-based automotive applications, such as autonomous driving, require the efficient real-time processing of huge amounts of data from different sensors, like camera, radar, and LiDAR. In the ZuSE-KI-AVF project, multiple university, and industry partners collaborate to develop a novel massive parallel processor architecture, based on a cus-tomized RISC-V host processor, and an efficient high-performance vertical vector coprocessor. In addition, a software development framework is also provided to efficiently program AI-based sensor processing applications. The proposed processor system was verified and evaluated on a state-of-the-art UltraScale+ FPGA board, reaching a processing performance of up to 126.9 FPS, while executing the YOLO-LITE CNN on 224x224 input images. Further optimizations of the FPGA design and the realization of the processor system on a 22nm FDSOI CMOS technology are planned.
2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 - Proceedings
year
2023
publisher
IEEE
isbn
9798350396249
comment
Funding Information: ACKNOWLEDGMENT The work is supported in part by the German Federal Ministry of Education and Research (BMBF) within the project ZuSE-KI-AVF under contract no. 16ME0379.
10.23919/date56975.2023.10136978
%0 Journal Article
%1 thieu2023kiavf
%A Thieu, Gia Bao
%A Gesper, Sven
%A Payá-Vayá, Guillermo
%A Riggers, Christoph
%A Renke, Oliver
%A Fiedler, Till Niklas
%A Marten, Jakob
%A Stuckenberg, Tobias
%A Blume, Holger
%A Weis, Christian
%A Steinert, Lukas
%A Sudarshan, Chirag
%A Wehn, Norbert
%A Reimann, Lennart M.
%A Leupers, Rainer
%A Beyer, Michael
%A Köhler, Daniel
%A Jauch, Alisa
%A Borrmann, Jan Micha
%A Jaberansari, Setareh
%A Berthold, Tim
%A Blawat, Meinolf
%A Kock, Markus
%A Schewior, Gregor
%A Benndorf, Jens
%A Kautz, Frederik
%A Bluethgen, Hans-Martin
%A Sauer, Christian
%B 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 - Proceedings
%D 2023
%I IEEE
%K AI ASIC FPGA RISC-V acceleration hardware-software myown processing processor sensor system vector vertical
%R 10.23919/date56975.2023.10136978
%T ZuSE KI-AVF
%U http://www.scopus.com/inward/record.url?scp=85162648667&partnerID=8YFLogxK
%X Modern and future AI-based automotive applications, such as autonomous driving, require the efficient real-time processing of huge amounts of data from different sensors, like camera, radar, and LiDAR. In the ZuSE-KI-AVF project, multiple university, and industry partners collaborate to develop a novel massive parallel processor architecture, based on a cus-tomized RISC-V host processor, and an efficient high-performance vertical vector coprocessor. In addition, a software development framework is also provided to efficiently program AI-based sensor processing applications. The proposed processor system was verified and evaluated on a state-of-the-art UltraScale+ FPGA board, reaching a processing performance of up to 126.9 FPS, while executing the YOLO-LITE CNN on 224x224 input images. Further optimizations of the FPGA design and the realization of the processor system on a 22nm FDSOI CMOS technology are planned.
%@ 9798350396249
@article{thieu2023kiavf,
abstract = {Modern and future AI-based automotive applications, such as autonomous driving, require the efficient real-time processing of huge amounts of data from different sensors, like camera, radar, and LiDAR. In the ZuSE-KI-AVF project, multiple university, and industry partners collaborate to develop a novel massive parallel processor architecture, based on a cus-tomized RISC-V host processor, and an efficient high-performance vertical vector coprocessor. In addition, a software development framework is also provided to efficiently program AI-based sensor processing applications. The proposed processor system was verified and evaluated on a state-of-the-art UltraScale+ FPGA board, reaching a processing performance of up to 126.9 FPS, while executing the YOLO-LITE CNN on 224x224 input images. Further optimizations of the FPGA design and the realization of the processor system on a 22nm FDSOI CMOS technology are planned.},
added-at = {2024-02-05T16:22:13.000+0100},
author = {Thieu, Gia Bao and Gesper, Sven and Payá-Vayá, Guillermo and Riggers, Christoph and Renke, Oliver and Fiedler, Till Niklas and Marten, Jakob and Stuckenberg, Tobias and Blume, Holger and Weis, Christian and Steinert, Lukas and Sudarshan, Chirag and Wehn, Norbert and Reimann, Lennart M. and Leupers, Rainer and Beyer, Michael and Köhler, Daniel and Jauch, Alisa and Borrmann, Jan Micha and Jaberansari, Setareh and Berthold, Tim and Blawat, Meinolf and Kock, Markus and Schewior, Gregor and Benndorf, Jens and Kautz, Frederik and Bluethgen, Hans-Martin and Sauer, Christian},
biburl = {https://www.bibsonomy.org/bibtex/2d0de2be05ed8380d2ab957eef2d4a61d/fabcho},
booktitle = {2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 - Proceedings},
comment = {Funding Information: ACKNOWLEDGMENT The work is supported in part by the German Federal Ministry of Education and Research (BMBF) within the project ZuSE-KI-AVF under contract no. 16ME0379.
10.23919/date56975.2023.10136978},
doi = {10.23919/date56975.2023.10136978},
interhash = {b99056be11f1dcfbb1d4faeb80e85a4d},
intrahash = {d0de2be05ed8380d2ab957eef2d4a61d},
isbn = {9798350396249},
keywords = {AI ASIC FPGA RISC-V acceleration hardware-software myown processing processor sensor system vector vertical},
publisher = {IEEE},
timestamp = {2024-03-05T15:37:31.000+0100},
title = {ZuSE KI-AVF},
url = {http://www.scopus.com/inward/record.url?scp=85162648667&partnerID=8YFLogxK},
year = 2023
}