%0 Conference Paper %1 conf/hpec/SingapuraKP16 %A Singapura, Shreyas G. %A Kannan, Rajgopal %A Prasanna, Viktor K. %B HPEC %D 2016 %I IEEE %K dblp %P 1-7 %T On-chip memory efficient data layout for 2D FFT on 3D memory integrated FPGA. %U http://dblp.uni-trier.de/db/conf/hpec/hpec2016.html#SingapuraKP16 %@ 978-1-5090-3525-0

@inproceedings{conf/hpec/SingapuraKP16, added-at = {2016-12-07T00:00:00.000+0100}, author = {Singapura, Shreyas G. and Kannan, Rajgopal and Prasanna, Viktor K.}, biburl = {https://www.bibsonomy.org/bibtex/2eb17356136693eaa037db99d4c6a058a/dblp}, booktitle = {HPEC}, crossref = {conf/hpec/2016}, ee = {http://dx.doi.org/10.1109/HPEC.2016.7761606}, interhash = {32f447aa92f1cb3ba8a339952a741ab6}, intrahash = {eb17356136693eaa037db99d4c6a058a}, isbn = {978-1-5090-3525-0}, keywords = {dblp}, pages = {1-7}, publisher = {IEEE}, timestamp = {2016-12-08T11:38:52.000+0100}, title = {On-chip memory efficient data layout for 2D FFT on 3D memory integrated FPGA.}, url = {http://dblp.uni-trier.de/db/conf/hpec/hpec2016.html#SingapuraKP16}, year = 2016 }