%0 Journal Article %1 journals/tcad/PomeranzR05 %A Pomeranz, Irith %A Reddy, Sudhakar M. %D 2005 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 2 %P 288-294 %T On masking of redundant faults in synchronous sequential circuits with design-for-testability logic. %U http://dblp.uni-trier.de/db/journals/tcad/tcad24.html#PomeranzR05 %V 24

@article{journals/tcad/PomeranzR05, added-at = {2020-09-24T00:00:00.000+0200}, author = {Pomeranz, Irith and Reddy, Sudhakar M.}, biburl = {https://www.bibsonomy.org/bibtex/2f5eaf1758e7e086e907e464f3bdcf85e/dblp}, ee = {https://doi.org/10.1109/TCAD.2004.840551}, interhash = {e2157e88e2dc4a352f32a68ae4972975}, intrahash = {f5eaf1758e7e086e907e464f3bdcf85e}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 2, pages = {288-294}, timestamp = {2020-09-25T11:48:41.000+0200}, title = {On masking of redundant faults in synchronous sequential circuits with design-for-testability logic.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad24.html#PomeranzR05}, volume = 24, year = 2005 }