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Disambiguation of "Reddy, Sudhakar M."

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On masking of redundant faults in synchronous sequential circuits with design-for-testability logic.

, and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (2): 288-294 (2005)

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Sudhakar Peddireddi

Padhmanand Sudhakar

Edamakanti Chandrakanth Reddy

Malgi Prasad Reddy

Martin Reddy

 

Other publications of authors with the same name

Random error and burst correction by iterated codes., and . IEEE Trans. Inf. Theory, 18 (1): 182-185 (1972)Random Test Generation With Input Cube Avoidance., and . IEEE Trans. Very Large Scale Integr. Syst., 17 (1): 45-54 (2009)A Repair-for-Diagnosis Methodology for Logic Circuits., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (11): 2254-2267 (2018)Path Selection for Transition Path Delay Faults., and . IEEE Trans. Very Large Scale Integr. Syst., 18 (3): 401-409 (2010)Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units., and . IEEE Trans. Very Large Scale Integr. Syst., 9 (5): 679-689 (2001)Embedded Totally Self-Checking Checkers: A Practical Design., and . IEEE Des. Test Comput., 7 (4): 5-12 (1990)On diagnosis of pattern-dependent delay faults., and . DAC, page 59-62. ACM, (2000)Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits., , , and . DAC, page 102-106. ACM Press, (1993)Fault Simulation under the Multiple Observation Time Approach using Backward Implications., and . DAC, page 608-613. ACM Press, (1997)Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences., and . DAC, page 754-759. ACM Press, (1999)