Abstract
Building software systems that are easier to use implies addressing the issue of increasing complexities in managing processes and communication between processes. In order to manage complexity, it is very important to have tools, notation, and methodologies which support the designer's work during design resolution. This paper introduces Extended Statecharts as a comprehensive modelling mechanism for high-level systems design. Extended Statecharts allow for the implicit representation of declarable, problem-specific system soft failures, thereby allowing for failure related information to be incorporated into the highlevel system design. Temporal logic is used for verification of important design properties. An example of an assembly process is used to illustrate the capabilities of Extended Statecharts.
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