%0 Journal Article %1 journals/iet-cds/YuwonoHYCL14 %A Yuwono, Sigit %A Han, Seok-Kyun %A Yoon, Giwan %A Cho, Han-Jin %A Lee, Sang-Gug %D 2014 %J IET Circuits Devices Syst. %K dblp %N 2 %P 73-81 %T Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array. %U http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds8.html#YuwonoHYCL14 %V 8

@article{journals/iet-cds/YuwonoHYCL14, added-at = {2022-11-02T00:00:00.000+0100}, author = {Yuwono, Sigit and Han, Seok-Kyun and Yoon, Giwan and Cho, Han-Jin and Lee, Sang-Gug}, biburl = {https://www.bibsonomy.org/bibtex/21442bb331c200d39b72f40d1b73a613c/dblp}, ee = {https://doi.org/10.1049/iet-cds.2013.0175}, interhash = {70524c708bc21bdecf52968c50fd2889}, intrahash = {1442bb331c200d39b72f40d1b73a613c}, journal = {IET Circuits Devices Syst.}, keywords = {dblp}, number = 2, pages = {73-81}, timestamp = {2024-04-08T16:07:19.000+0200}, title = {Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array.}, url = {http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds8.html#YuwonoHYCL14}, volume = 8, year = 2014 }