%0 Conference Paper %1 conf/hipeac/GurkaynakSM0MB17 %A Gürkaynak, Frank K. %A Schilling, Robert %A Muehlberghuber, Michael %A Conti, Francesco %A Mangard, Stefan %A Benini, Luca %B CS2@HiPEAC %D 2017 %E Brorsson, Mats %E Lu, Zhonghai %E Agosta, Giovanni %E Barenghi, Alessandro %E Pelosi, Gerardo %I ACM %K %P 19-24 %T Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS. %U http://dblp.uni-trier.de/db/conf/hipeac/cs2017.html#GurkaynakSM0MB17 %@ 978-1-4503-4869-0

@inproceedings{conf/hipeac/GurkaynakSM0MB17, added-at = {2023-12-13T01:35:10.000+0100}, author = {Gürkaynak, Frank K. and Schilling, Robert and Muehlberghuber, Michael and Conti, Francesco and Mangard, Stefan and Benini, Luca}, biburl = {https://www.bibsonomy.org/bibtex/242d529f64f0acbd7fed05dcf908a5f75/admin}, booktitle = {CS2@HiPEAC}, crossref = {conf/hipeac/2017cs}, editor = {Brorsson, Mats and Lu, Zhonghai and Agosta, Giovanni and Barenghi, Alessandro and Pelosi, Gerardo}, ee = {https://doi.org/10.1145/3031836.3031840}, interhash = {73a177765fb239467d64a98b9d607ffc}, intrahash = {42d529f64f0acbd7fed05dcf908a5f75}, isbn = {978-1-4503-4869-0}, keywords = {}, pages = {19-24}, publisher = {ACM}, timestamp = {2023-12-13T01:35:10.000+0100}, title = {Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/hipeac/cs2017.html#GurkaynakSM0MB17}, year = 2017 }