%0 Conference Paper %1 DT_ICSES %A Zielinski, L. %A Rutkowski, J. %B ICSES'04 International Conference on Signals and Electronic Systems %C Poznan University of Technology, Poznan, Poland %D 2004 %K Expression Gene Programming, algorithms, analog circuits, computation, design evolutionary genetic optimization programming, tolerancing, %T Design Tolerancing with Utilization of Gene Expression Programming and Genetic Algorithm %U http://www.funzone.pl/Articles/DT_ICSES.pdf %X Design Tolerancing (DT). This issue plays huge role in design of analog circuits. Because practically it is impossible to obtain optimum solution by mathematically described computational methods, this problem is numbered to NP difficult category. Optimum tolerances of analogue circuit parameters such as resistance, capacitance and inductance, are determined based on Genetic Algorithms and new evolutionary technique i.e. Gene Expression Programming (GEP). To explain and assess the new DT method, two practical examples are presented.

@inproceedings{DT_ICSES, abstract = {Design Tolerancing (DT). This issue plays huge role in design of analog circuits. Because practically it is impossible to obtain optimum solution by mathematically described computational methods, this problem is numbered to NP difficult category. Optimum tolerances of analogue circuit parameters such as resistance, capacitance and inductance, are determined based on Genetic Algorithms and new evolutionary technique i.e. Gene Expression Programming (GEP). To explain and assess the new DT method, two practical examples are presented.}, added-at = {2008-06-19T17:35:00.000+0200}, address = {Poznan University of Technology, Poznan, Poland}, author = {Zielinski, L. and Rutkowski, J.}, biburl = {https://www.bibsonomy.org/bibtex/2226c582cea14030ed900e52a06ff0b2d/brazovayeye}, booktitle = {ICSES'04 International Conference on Signals and Electronic Systems}, interhash = {bfec9ae26aeda063b9342f770929c9de}, intrahash = {226c582cea14030ed900e52a06ff0b2d}, keywords = {Expression Gene Programming, algorithms, analog circuits, computation, design evolutionary genetic optimization programming, tolerancing,}, month = {13-15 September}, notes = {Silesian University of Technology, POLAND}, organisation = {PTETiS, IEEE, EURASIP, Polish Academy of Sciences}, timestamp = {2008-06-19T17:55:56.000+0200}, title = {Design Tolerancing with Utilization of Gene Expression Programming and Genetic Algorithm}, url = {http://www.funzone.pl/Articles/DT_ICSES.pdf}, year = 2004 }