Inproceedings,
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.
S. Clerc, M. Saligane, F. Abouzeid, M. Cochet, J. Daveau, C. Bottoni, D. Bol, J. Vos, D. Zamora, B. Coeffic, D. Soussan, D. Croain, M. Naceur, P. Schamberger, P. Roche, and D. Sylvester.ISSCC, page 1-3. IEEE, (2015)
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- BibTeX key
- conf/isscc/ClercSACDBBVZCS15
- entry type
- inproceedings
- booktitle
- ISSCC
- year
- 2015
- pages
- 1-3
- publisher
- IEEE
- crossref
- conf/isscc/2015
- ee
- https://doi.org/10.1109/ISSCC.2015.7062970
- isbn
- 978-1-4799-6224-2
- url
- http://dblp.uni-trier.de/db/conf/isscc/isscc2015.html#ClercSACDBBVZCS15
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- please select -%0 Conference Paper
%1 conf/isscc/ClercSACDBBVZCS15
%A Clerc, Sylvain
%A Saligane, Mehdi
%A Abouzeid, Fady
%A Cochet, Martin
%A Daveau, Jean-Marc
%A Bottoni, Cyril
%A Bol, David
%A Vos, Julien De
%A Zamora, Dominique
%A Coeffic, Benjamin
%A Soussan, Dimitri
%A Croain, Damien
%A Naceur, Mehdi
%A Schamberger, Pierre
%A Roche, Philippe
%A Sylvester, Dennis
%B ISSCC
%D 2015
%I IEEE
%K dblp
%P 1-3
%T 8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2015.html#ClercSACDBBVZCS15
%@ 978-1-4799-6224-2
@inproceedings{conf/isscc/ClercSACDBBVZCS15,
added-at = {2022-04-09T00:00:00.000+0200},
author = {Clerc, Sylvain and Saligane, Mehdi and Abouzeid, Fady and Cochet, Martin and Daveau, Jean-Marc and Bottoni, Cyril and Bol, David and Vos, Julien De and Zamora, Dominique and Coeffic, Benjamin and Soussan, Dimitri and Croain, Damien and Naceur, Mehdi and Schamberger, Pierre and Roche, Philippe and Sylvester, Dennis},
biburl = {https://www.bibsonomy.org/bibtex/2a0218a4f6d753b783f5485d6b8a27e11/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2015},
ee = {https://doi.org/10.1109/ISSCC.2015.7062970},
interhash = {c7819c64c34072b96e95b07cd6f1ed8a},
intrahash = {a0218a4f6d753b783f5485d6b8a27e11},
isbn = {978-1-4799-6224-2},
keywords = {dblp},
pages = {1-3},
publisher = {IEEE},
timestamp = {2024-04-10T11:03:36.000+0200},
title = {8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2015.html#ClercSACDBBVZCS15},
year = 2015
}