%0 Conference Paper %1 conf/vlsid/MadathilRCMGBU00 %A Madathil, Karthikeyan %A Rao, Jagdish C. %A G., Subash Chandar %A Menon, Amitabh %A Gautam, Avinash K. %A Brahme, Amit M. %A Udayakumar, H. %B VLSI Design %D 2000 %I IEEE Computer Society %K dblp %P 468- %T A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2000.html#MadathilRCMGBU00 %@ 0-7695-0487-6

@inproceedings{conf/vlsid/MadathilRCMGBU00, added-at = {2023-03-24T00:00:00.000+0100}, author = {Madathil, Karthikeyan and Rao, Jagdish C. and G., Subash Chandar and Menon, Amitabh and Gautam, Avinash K. and Brahme, Amit M. and Udayakumar, H.}, biburl = {https://www.bibsonomy.org/bibtex/21a3997834cd09f57a77584871c8d517f/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2000}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812651}, interhash = {e1ae401ee1c0f4b02e39180db6c7de6f}, intrahash = {1a3997834cd09f57a77584871c8d517f}, isbn = {0-7695-0487-6}, keywords = {dblp}, pages = {468-}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:19:01.000+0200}, title = {A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2000.html#MadathilRCMGBU00}, year = 2000 }