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Disambiguation of "Rao, Jagdish C."

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A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores.

, , , , , , and . VLSI Design, page 468-. IEEE Computer Society, (2000)

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Jagdish Ramakrishnan

Jagdish Trivedi

Jagdish Shah

Jagdish Mathur

Jagdish Patwardhan

 

Other publications of authors with the same name

Clock gating for power optimization in ASIC design cycle theory & practice., , , , , and . ISLPED, page 307-308. ACM, (2008)Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon., , , , , , , , , and 3 other author(s). ASP-DAC/VLSI Design, page 781-788. IEEE Computer Society, (2002)A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores., , , , , , and . VLSI Design, page 468-. IEEE Computer Society, (2000)A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors., , , and . VLSI Design, page 346-349. IEEE Computer Society, (1999)Clock gating effectiveness metrics: Applications to power optimization., , , , and . ISQED, page 482-487. IEEE Computer Society, (2009)Enabling Quality and Schedule Predictability in SoC Design using HandoffQC., , , and . ISQED, page 769-774. IEEE Computer Society, (2006)Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions., , , , and . VLSI Design, page 525-530. IEEE Computer Society, (2009)A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology., , , , , , and . ICCD, page 340-347. IEEE Computer Society, (1999)