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%0 Conference Paper
%1 conf/iscas/RaghavanAACML07
%A Raghavan, Praveen
%A Ayala, José L.
%A Atienza, David
%A Catthoor, Francky
%A Micheli, Giovanni De
%A López-Vallejo, Marisa
%B ISCAS
%D 2007
%I IEEE
%K dblp
%P 121-124
%T Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.
%U http://dblp.uni-trier.de/db/conf/iscas/iscas2007.html#RaghavanAACML07
%@ 1-4244-0921-7
@inproceedings{conf/iscas/RaghavanAACML07,
added-at = {2022-10-02T00:00:00.000+0200},
author = {Raghavan, Praveen and Ayala, José L. and Atienza, David and Catthoor, Francky and Micheli, Giovanni De and López-Vallejo, Marisa},
biburl = {https://www.bibsonomy.org/bibtex/27c93d35dea15d59b1e9d1e9c8454826e/dblp},
booktitle = {ISCAS},
crossref = {conf/iscas/2007},
ee = {https://www.wikidata.org/entity/Q60244840},
interhash = {e87f3514021bba3159c2eb508bc0fc3f},
intrahash = {7c93d35dea15d59b1e9d1e9c8454826e},
isbn = {1-4244-0921-7},
keywords = {dblp},
pages = {121-124},
publisher = {IEEE},
timestamp = {2024-04-10T17:45:36.000+0200},
title = {Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.},
url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2007.html#RaghavanAACML07},
year = 2007
}