%0 Journal Article %1 journals/tc/LiuS91 %A Liu, Jyh-Charn %A Shin, Kang G. %D 1991 %J IEEE Trans. Computers %K dblp %N 10 %P 1153-1159 %T A RAM Architecture for Concurrent Access and On-Chip Testing. %U http://dblp.uni-trier.de/db/journals/tc/tc40.html#LiuS91 %V 40

@article{journals/tc/LiuS91, added-at = {2015-12-22T00:00:00.000+0100}, author = {Liu, Jyh-Charn and Shin, Kang G.}, biburl = {https://www.bibsonomy.org/bibtex/2882ab164fea86872b66b3e5950999fa7/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/12.93748}, interhash = {f5ff6b526f16674e24b7f50b03d18bba}, intrahash = {882ab164fea86872b66b3e5950999fa7}, journal = {IEEE Trans. Computers}, keywords = {dblp}, number = 10, pages = {1153-1159}, timestamp = {2015-12-24T12:09:20.000+0100}, title = {A RAM Architecture for Concurrent Access and On-Chip Testing.}, url = {http://dblp.uni-trier.de/db/journals/tc/tc40.html#LiuS91}, volume = 40, year = 1991 }