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Employing Transactional Memory and Helper Threads to Speedup Dijkstra's Algorithm.

, , , and . ICPP, page 388-395. IEEE Computer Society, (2009)

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Facilitating efficient synchronization of asymmetric threads on hyper-threaded processors., and . IPDPS, page 1-8. IEEE, (2008)Early experiences on accelerating Dijkstra's algorithm using transactional memory., , , and . IPDPS, page 1-8. IEEE, (2009)Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures., , , and . Panhellenic Conference on Informatics, volume 3746 of Lecture Notes in Computer Science, page 600-610. Springer, (2005)Employing Transactional Memory and Helper Threads to Speedup Dijkstra's Algorithm., , , and . ICPP, page 388-395. IEEE Computer Society, (2009)Understanding the Performance of Sparse Matrix-Vector Multiplication., , , , and . PDP, page 283-292. IEEE Computer Society, (2008)PLQCD library for Lattice QCD on multi-core machines., , , , , and . CoRR, (2014)Performance evaluation of the sparse matrix-vector multiplication on modern architectures., , , , and . J. Supercomput., 50 (1): 36-77 (2009)Exploring the performance limits of simultaneous multithreading for memory intensive applications., , , and . J. Supercomput., 44 (1): 64-97 (2008)LCA: a memory link and cache-aware co-scheduling approach for CMPs., , , , , and . PACT, page 469-470. ACM, (2014)Exploring the Capacity of a Modern SMT Architecture to Deliver High Scientific Application Performance., , , and . HPCC, volume 4208 of Lecture Notes in Computer Science, page 180-189. Springer, (2006)