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Disambiguation of "Kuppannagari, Sanmukh R."

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A High Throughput Parallel Hash Table on FPGA using XOR-based Memory.

, , , , and . HPEC, page 1-7. IEEE, (2020)

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Other publications of authors with the same name

How to Avoid Zero-Spacing in Fractionally-Strided Convolution? A Hardware-Algorithm Co-Design Methodology., , , and . HiPC, page 81-90. IEEE, (2021)A High Throughput Parallel Hash Table on FPGA using XOR-based Memory., , , , and . HPEC, page 1-7. IEEE, (2020)NTTGen: a framework for generating low latency NTT implementations on FPGA., , , and . CF, page 30-39. ACM, (2022)Bandwidth Efficient Homomorphic Encrypted Matrix Vector Multiplication Accelerator on FPGA., , , and . FPT, page 1-9. IEEE, (2022)Efficient Generation of Energy and Performance Pareto Front for FPGA Designs (Abstract Only)., and . FPGA, page 273. ACM, (2015)PPOAccel: A High-Throughput Acceleration Framework for Proximal Policy Optimization., , , and . IEEE Trans. Parallel Distributed Syst., 33 (9): 2066-2078 (2022)FPGA Accelerator for Homomorphic Encrypted Sparse Convolutional Neural Network Inference., , , and . FCCM, page 1-9. IEEE, (2022)Efficient Neighbor-Sampling-based GNN Training on CPU-FPGA Heterogeneous Platform., , , and . HPEC, page 1-7. IEEE, (2021)Accelerating Proximal Policy Optimization on CPU-FPGA Heterogeneous Platforms., , and . FCCM, page 19-27. IEEE, (2020)NO-LESS: Near optimal curtailment strategy selection for net load balancing in micro grids., , and . ISGT, page 1-5. IEEE, (2018)