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Table look-up based compact modeling for on-chip interconnect timing and noise analysis., , , , , , and . ISCAS (4), page 668-671. IEEE, (2003)Model and analysis for combined package and on-chip power grid simulation., , , , , and . ISLPED, page 179-184. ACM, (2000)Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions., , , and . DAC, page 71-76. ACM, (2005)Circuit optimization using statistical static timing analysis., , , and . DAC, page 321-324. ACM, (2005)Computation and Refinement of Statistical Bounds on Circuit Delay., , , and . DAC, page 348-353. ACM, (2003)Incremental Criticality and Yield Gradients., , and . DATE, page 1130-1135. ACM, (2008)Static timing: Back to our roots., , , , and . ASP-DAC, page 310-315. IEEE, (2008)Accurate delay computation for noisy waveform shapes., , and . ICCAD, page 947-953. IEEE Computer Society, (2005)Noise propagation and failure criteria for VLSI designs., , , , , , , and . ICCAD, page 587-594. ACM / IEEE Computer Society, (2002)A precorrected-FFT method for simulating on-chip inductance., , , , , , and . ICCAD, page 221-227. ACM / IEEE Computer Society, (2002)