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Custom-instruction synthesis for extensible-processor platforms.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (2): 216-228 (2004)

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Energy and execution time analysis of a software-based trusted platform module., , , and . DATE, page 1128-1133. EDA Consortium, San Jose, CA, USA, (2007)A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (11): 2035-2045 (2007)Automated Energy/Performance Macromodeling of Embedded Software., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (3): 542-552 (2007)Use of Computation-Unit Integrated Memories in High-Level Synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (10): 1969-1989 (2006)A framework for testing core-based systems-on-a-chip., , and . ICCAD, page 385-390. IEEE Computer Society, (1999)Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing., , , , , and . ITC, page 509-513. IEEE, (2022)Power-aware test: Challenges and solutions.. ITC, page 1-10. IEEE Computer Society, (2007)At-speed capture power reduction using layout-aware granular clock gate enable controls., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2014)Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits., , , and . VLSI Design, page 193-198. IEEE Computer Society, (1998)Transient Power Management Through High Level Synthesis., , , and . ICCAD, page 545-552. IEEE Computer Society, (2001)