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Disambiguation of "Iyengar, Vikram"

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Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints.

, , , and . ITC, page 1159-1168. IEEE Computer Society, (2002)

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Narayanaswamy Iyengar

Vikram Mehta

Iyengar Chokkana

Vikram Menon

Vikram Mavalankar

 

Other publications of authors with the same name

Performance verification of high-performance ASICs using at-speed structural test., , , , , , , , , and . ACM Great Lakes Symposium on VLSI, page 247-252. ACM, (2006)On the Use of k-tuples for SoC Test Schedule Representation., and . ITC, page 539-548. IEEE Computer Society, (2002)Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints., , , and . ITC, page 1159-1168. IEEE Computer Society, (2002)Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking., , and . VTS, page 46-51. IEEE Computer Society, (2006)Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters., , and . VTS, page 22-27. IEEE Computer Society, (1999)A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization., , , and . DATE, page 11188-11190. IEEE Computer Society, (2003)Defect-Oriented Test for Ultra-Low DPM., and . Asian Test Symposium, page 455. IEEE Computer Society, (2005)Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking., and . DATE, page 652-657. European Design and Automation Association, Leuven, Belgium, (2006)Test cost reduction for SOCs using virtual TAMs and lagrange multipliers., , , and . DAC, page 738-743. ACM, (2003)A flexible and scalable methodology for GHz-speed structural test., , and . DAC, page 314-319. ACM, (2006)