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Disambiguation of "Ishihara, Shota"

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An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture.

, , , and . ASP-DAC, page 89-90. IEEE, (2011)

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Aeka Ishihara

Hirofumi Ishihara

Shota Okujava

 

Other publications of authors with the same name

An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture., , , and . ERSA, page 271-274. CSREA Press, (2010)Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture., , and . IEICE Trans. Electron., 91-C (9): 1419-1426 (2008)A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals?, , , and . J. Multiple Valued Log. Soft Comput., 17 (5-6): 553-580 (2011)An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture., , , and . IEICE Trans. Electron., 93-C (8): 1338-1348 (2010)An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters., , , and . ERSA, page 145-150. CSREA Press, (2009)A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic., , , and . ERSA, page 271-274. CSREA Press, (2009)A low-power FPGA based on autonomous fine-grain power-gating., , and . ASP-DAC, page 119-120. IEEE, (2009)A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (8): 1394-1406 (2011)A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals., , , and . IEICE Trans. Inf. Syst., 93-D (8): 2134-2144 (2010)Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture., , , , and . IEICE Trans. Electron., 94-C (10): 1669-1679 (2011)