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Disambiguation of "Ioannou, Aggelos"

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HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware - ECOSCALE.

, , , , , and . ARC, volume 10824 of Lecture Notes in Computer Science, page 724-736. Springer, (2018)

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Ekaterini Ioannou

Aggelos Calogirou

Panagiota Ioannou

Aggelos Kapellos

Nearchos Ioannou

 

Other publications of authors with the same name

Implementation and Impact of an Ultra-Compact Multi-FPGA Board for Large System Prototyping., , , , , , , , , and 4 other author(s). H2RC@SC, page 34-41. IEEE, (2019)Early Results of Mapping Industrial Applications on Heterogeneous HPC Systems: The OPTIMA Project., , , , , , , , , and 7 other author(s). CF, page 304-308. ACM, (2023)Low-latency Communication in RISC-V Clusters., , , , , , , , , and . HPC Asia, page 73-83. ACM, (2024)The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack., , , , , , , , , and 14 other author(s). CoRR, (2023)Moving Compute towards Data in Heterogeneous multi-FPGA Clusters using Partial Reconfiguration and I/O Virtualisation., , , , , , and . FPT, page 221-226. IEEE, (2020)Efficient Convolutional Neural Network Weight Compression for Space Data Classification on Multi-fpga Platforms., , , , , , , and . ICASSP, page 3917-3921. IEEE, (2019)HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware - ECOSCALE., , , , , and . ARC, volume 10824 of Lecture Notes in Computer Science, page 724-736. Springer, (2018)Prototyping Efficient Interprocessor Communication Mechanisms., , , , , , , , and . ICSAMOS, page 26-33. IEEE, (2007)Pipelined heap (priority queue) management for advanced scheduling in high-speed networks., and . IEEE/ACM Trans. Netw., 15 (2): 450-461 (2007)Pipelined heap (priority queue) management for advanced scheduling in high-speed networks., and . ICC, page 2043-2047. IEEE, (2001)