From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM., , , и . CICC, стр. 451-454. IEEE, (2005)A Scalable Massively Parallel Processor for Real-Time Image Processing., , , , , , , , , и 9 other автор(ы). IEEE J. Solid State Circuits, 46 (10): 2363-2373 (2011)A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory., , , , , , , и . IEEE J. Solid State Circuits, 42 (4): 853-861 (2007)A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros., , , , , , , , , и 2 other автор(ы). IEICE Trans. Electron., 88-C (10): 2020-2027 (2005)Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications., , , , и . COOL Chips, стр. 1-3. IEEE Computer Society, (2017)CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table image coding example., , , , , , , и . ISCAS (5), стр. 5202-5205. IEEE, (2005)Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine., , , , , , , и . ISCAS, стр. 525-528. IEEE, (2007)Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh., , , , , , , , и . IEICE Trans. Electron., 88-C (4): 622-629 (2005)A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features., , , , и . IEICE Trans. Electron., 88-C (6): 1332-1342 (2005)The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture., , , , , , , , , и 5 other автор(ы). IEEE J. Solid State Circuits, 42 (1): 183-192 (2007)