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Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance., , , , , , and . CoRR, (2018)High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems., , , , and . CoRR, (2018)RowClone: Accelerating Data Movement and Initialization Using DRAM., , , , , , , , , and 1 other author(s). CoRR, (2018)A Modern Primer on Processing in Memory., , , and . CoRR, (2020)Mosaic: Enabling Application-Transparent Support for Multiple Page Sizes in Throughput Processors., , , , , , and . ACM SIGOPS Oper. Syst. Rev., 52 (1): 27-44 (2018)Application-to-core mapping policies to reduce memory system interference in multi-core systems., , , , and . HPCA, page 107-118. IEEE Computer Society, (2013)Design and Evaluation of Hierarchical Rings with Deflection Routing., , , , , , , and . SBAC-PAD, page 230-237. IEEE Computer Society, (2014)Differentiating Cache Files for Fine-grain Management to Improve Mobile Performance and Lifetime., , , , , , and . HotStorage, USENIX Association, (2020)CoNDA: efficient cache coherence support for near-data accelerators., , , , , , , , , and 1 other author(s). ISCA, page 629-642. ACM, (2019)Binary Star: Coordinated Reliability in Heterogeneous Memory Systems for High Performance and Scalability., , , , and . MICRO, page 807-820. ACM, (2019)